1. Technical Field
Various embodiments of the present disclosure described herein generally relate to a semiconductor integrated circuit, and more particularly, to a device for generating a clock in a semiconductor integrated circuit.
2. Related Art
In general, the activation speed of semiconductor integrated circuits has been improved by activating the semiconductor integrated circuits using clocks. To increase activation speed, semiconductor integrated circuits are provided with a clock buffer and use an external clock input after buffering. In some cases, the semiconductor integrated circuits generate and use, by themselves, an internal clock that has been corrected in the phase difference from an external clock by a clock generator, such as a DLL (Delay Locked Loop) circuit or a PLL (Phase. Locked Loop) circuit.
Currently, the activation speed of semiconductor integrated circuits gradually increases, and accordingly, conventional semiconductor integrated circuits synchronize data with each phase by dividing a phase of an internal clock into several phases to generate a multi-phase internal clock. Accordingly, the internal clock is implemented as a set of a plurality of clocks with a predetermined phase difference.
More recently, a plurality of channels for transmitting signals between semiconductor integrated circuits have been provided, in which the channels may be activated in different frequency domains. However, each channel is typically provided with a clock generator to accomplish the operation. As a result, this deteriorates both an area margin and power efficiency of the semiconductor integrated circuits.
Furthermore, typical semiconductor integrated circuits generate a clock by combining rising edges of the clocks included in a multi-phase internal clock; however, this configuration is problematic because the frequency band is limited to implementing a low-frequency operation mode. Typical semiconductor integrated circuits are required to lower the frequency of each clock before combining the rising edges of the clocks in the low-frequency operation mode because there is a certain limit in lowering the frequency of the clocks.
As described above, since a clock generator should usually be provided for each channel in semiconductor integrated circuits, efficient application was difficult in terms of area and power and it was difficult to implement an appropriate operation at the low-frequency operation mode. Therefore, it is desirable to have an improved device for generating a clock that achieves high integration and low power consumption in a semiconductor integrated circuit.